1. Field of the Invention
The present invention relates to a polysilicon thin film transistor device and a method of fabricating a polysilicon thin film transistor device, and more particularly, to a bottom-gated silicon thin film transistor device and a method of fabricating a bottom-gated silicon thin film transistor device.
2. Description of the Related Art
As demand increases for flat panel displays having slim profiles, light weight, and low power consumption, development of new liquid crystal display (LCD) devices having superior color reproduction has increased. In general, LCD devices include two substrates facing each other, wherein electrodes are formed on facing surfaces of the substrates, and a liquid crystal material is injected into a space defined between the substrates. Accordingly, the LCD device displays images by changing alignment of liquid crystal molecules within the liquid crystal material by an electric field generated by voltages applied to the electrodes in order to vary a light transmittance of the liquid crystal material.
Among the different types of LCD devices, active matrix LCD (AM-LCD) devices are being developed due to their high image resolution and superior ability to display moving images. In the AM-LCD device, pixel electrodes are formed on a lower thin film transistor (TFT) array substrate, and a common electrode is formed on an upper color filter substrate. By controlling voltages applied between the pixel electrodes and the common electrode, liquid crystal molecules of the AM-LCD are driven. Accordingly, the AM-LCD device has superior light transmittance and aperture ratio characteristics. In addition, since the common electrode of the AM-LCD device functions as a ground, failure of LC cells of the AM-LCD device to electrostatic discharge is prevented. The TFTs used in the AM-LCD device are classified as one of amorphous silicon TFTs and a polycrystalline silicon (i.e., polysilicon) TFTs depending on whether an active channel region functions using amorphous silicon or polysilicon.
The amorphous TFT is commonly used because it enables fabrication of large-sized displays, thereby resulting in high productivity. In addition, fabrication of the amorphous TFT includes low temperature deposition of the amorphous silicon at temperatures less than 350° C., and uses low priced insulator substrates. However, due to disordered atomic arrangement, weak Si—Si bonds, and dangling bonds of the amorphous silicon, hydrogenized amorphous silicon (a:Si—H) is used. But, a:Si—H becomes a metastable state when exposed to light or an electric field is applied, thereby causing instability. For example, when light is irradiated onto a:Si—H, field mobility and reliability deteriorate, thereby making it difficult to use amorphous silicon in driving circuitry of an LCD device. In addition, as resolution of an LCD panel of the LCD devices increases, pitch of contact pads used for connecting gate lines and data lines with a tape carrier package (TCP) decreases, thereby causing problems using TCP bonding processes.
Meanwhile, since the polysilicon TFT has a field mobility higher than that of the amorphous TFT, driving circuitry can be made directly onto a substrate, thereby reducing manufacturing costs for fabricating the driving circuitry and simplifying mounting processes. In addition, since field mobility of the polysilicon TFTs are 100 to 200 times greater than the field mobility of the amorphous silicon TFTs, the polysilicon TFTS have fast response times and superior stability against temperature and light. Moreover, the polysilicon TFTs have an advantage in that the driving circuitry may be formed on an identical substrate together with other device elements.
FIG. 1 is a plan view of a pixel region of an LCD device according to the related art. In FIG. 1, a plurality of parallel gate lines 111 and a plurality of parallel data lines 112 are arranged on a transparent substrate in a matrix configuration, thereby defining a plurality of pixel regions. A TFT including a semiconductor layer 116, a gate electrode 120, a source electrode 126, and a drain electrode 128 is formed at each crossing point of the gate and data lines 111 and 112, and a pixel electrode 134 electrically connected with the TFT is disposed within one of the pixel regions defined by the gate and data lines 111 and 112. The source electrode 126 and the drain electrode 128 electrically contact the semiconductor layer 116 through first and second contact holes 122a and 122b, and the drain electrode 128 electrically contacts the pixel electrode 134 through a contact hole 130. The semiconductor layer 116 is composed of polysilicon (p-Si), which is formed by depositing an amorphous silicon (a-Si) film on the substrate and annealing the deposited amorphous silicon film using a laser.
FIG. 2 is a cross sectional view along I-I′ of FIG. 1 according to the related art. In FIG. 2, a buffer layer 114 is formed along an entire surface of the substrate 100, and the gate electrode 120 is formed on the buffer layer 114. Then, a gate insulating film 118 is formed on the gate electrode 120 and the buffer layer 114, and a semiconductor layer 116 is formed on the gate insulating film 118.
Next, an interlayer insulating film 124 is formed to cover the semiconductor layer 116, and includes first and second contact holes 122a and 122b. Then, the source and drain electrodes 126 and 128 are formed on the interlayer insulating film 124 and within the first and second contact holes 122a and 122b, thereby connecting the source and drain electrodes 126 and 128 with the semiconductor layer 116 through the first and second contact holes 122a and 122b. 
Then, a passivation layer 132 having a drain contact hole 130 is formed on the source and drain electrodes 126 and 128 and the interlayer insulating film 124. Next, a pixel electrode 134 is formed on the passivation layer 132 and in the drain contact hole, and is connected to the drain electrode 128 through the drain contact hole 130.
In FIGS. 1 and 2, the gate electrode 120 and a gate line 111 are formed of the same metal material. However, the gate electrode 120 and the gate line 111 have a height difference that may result in creating an open circuit condition of the gate line during crystallization of the amorphous silicon.
FIG. 3 is a cross sectional view of a crystallization process according to the related art. In FIG. 3, the amorphous silicon film 116 is formed along an entire surface of the substrate 100 to a thickness of 300˜4,000 {hacek over (A)} by a plasma enhanced chemical vapor deposition (PECVD) method. Then, the amorphous silicon film 116 undergoes a hydrogen evolution at 400˜500° C. The hydrogen evolution is performed to remove hydrogen added during the deposition of the amorphous silicon film 120a, thereby preventing film ablation phenomenon during a subsequent laser annealing process. Then, the hydrogen evolution-treated amorphous silicon film 116 is annealed using a laser, and is crystallized.
In FIGS. 2 and 3, if a thickness of the gate electrode 120 is large, an open circuit condition may be created during the laser annealing process of the amorphous silicon film 116 at a stepped portion “A.” This is due to agglomeration of silicon atoms of the amorphous silicon film due to curvature of the stepped portion “A” while the amorphous silicon film is crystallized. Accordingly, the thickness of the gate electrode 120 must be appropriately thin. However, if the thickness of the gate electrode is too thin, data transmission (i.e., line delay) may be caused due to an increase in electrical resistance of the gate line while the gate line and the gate electrode are driven.